The invention is directed to a method for dividing the frequency of an alternating voltage with a non-whole-numbered division factor into a second frequency upon alternating generation of a first cycle group having a first periodicity by division with a first, whole-numbered, auxiliary division factor whose value lies above that of the division factor, and of a second cycle group having a second periodicity by division with a second, whole-numbered, auxiliary division factor whose value lies below that of the division factor.
Such a method is known for a switchable divider (dual modulus divider) that is presented in the "SP8000 Series High Speed Dividers Integrated Circuit Handbook", The Plessey Company plc, Nov. 1981, publication No. P.S. 1937, pages 140-143, incorporated herein.
The periodical, "IEEE Journal of Solid-State Circuits", April 1989, Vol. 24, No. 2, pages 256-266, incorporated herein, describes a sigma-delta modulation. In this type of modulation, amplitude values are integrated in the clock. When a threshold is reached, a pulse is output and the integrator is reset. The pulse repetition rate depends on the size of the individual amplitude value.
The periodical "ntz", 41 (1988) No. 10, pages 570-574, incorporated herein, describes a synchronous digital hierarchy SDH having a basic bit rate of 155.52 Mbit/s when signals both from the European as well as from the North American plesiochronic digital hierarchy PDH are transmitted in pulse frames called transport modules.
FIG. 1 of the present application shows a multiplex structure of the synchronous digital hierarchy SDH. AU means administrative unit, AUG means administrative unit group, C means container, STM means synchronous transport module, TU means tributary unit, TUG means tributary unit group, and VC means virtual container. The attached numbers or pairs of numbers n indicate the position in the multiplex structure. A is a region of higher order, B is a region of lower order.
Plesiochronic signals to be transmitted are periodically inserted into the container C-n during multiplexing with the assistance of positive pulse stuffing. Each of these containers is supplemented by the addition of a path overhead to form a virtual container VC-n. The chronological position of the first bytes thereof in the frame of a STM-N signal (N=1, 2, 4, 8, 12, 16) or of a virtual container of a higher hierarchy level is indicated by a pointer. A virtual container VC-11, VC-12, VC-2 or VC-3 can form a tributary unit TU-n together with the pointer allocated to it. A plurality of these having the same structure can in turn be combined to form a tributary unit group TUG-n that in turn has space in a virtual container VC-3 or VC-4. The latter is inserted into an administrative unit AU-3 or AU-4 that can be combined to form an administrative unit group AUG together with an administrative unit pointer. This administrative unit group AUG forms a STM-1 signal together with the section overhead. A plurality of these STM-1 signals form a STM-N signal. The method steps proceed in the opposite direction during demultiplexing. The numbers at the lines indicate how many times the frame parts are transmitted together.
No frequency-compensating stuffing procedures should be required in a synchronously operating network. Since, however, greater phase shifts due to fluctuations in cable running time given longer cable links must be avoided, and since, moreover, frequency deviations given losses of synchronization as well as given transitions to other networks must be compensated, the pointers have a further job.
It is not only a phase difference between virtual container and STM frame that is taken into consideration with the pointer; rather, frequency differences between a STM-N input and output signal or, respectively, network node clock, can also be compensated therewith on the basis of a positive/zero/negative pulse stuffing. For that purpose, the pointer is composed of a H1, or of a H2 and a H3 byte. The first two contain the actual pointer which indicates the position of the first byte of the virtual container and contains a stuffing information, and the H3 byte can be an information byte in frequency compensation procedures.
In the case of a frequency offset between the STM frame clock and the frame clock of the virtual container, the pointer must be occasionally modified, whereby either a positive or a negative stuffing byte or three thereof as well are provided in the STM frame for frequency compensation dependent on the position in the multiplex structure.
When the frame clock of the virtual container is too slow in comparison to the STM frame clock, then the start of the virtual container must be offset to a later time in chronological intervals within the frame. In such a compensation procedure, one or, respectively, three, dummy bytes are inserted into the useful information block following the section overhead, and the pointer is incremented (positive pulse stuffing) by a value step, whereby this contains a skip over three bytes.
When the frame clock of the virtual container is too fast in comparison to the STM-N frame clock, then the start of the virtual container must be offset to an earlier time within the STM frame. In such a compensation procedure, the pointer value is deincremented by a value step and one or three additional information bytes must be additionally transmitted (negative pulse stuffing). This is inserted into the one or into the three H3 bytes of the pointer--the pointer action byte.
In addition to containing the actual pointer value, the first two pointer bytes contain the information as to whether stuffing was carried out positively, zero, or negatively.
Given a cross-connect means wherein virtual containers of the types VC-11, VC-12, VC-2 or VC-3 (in the region of the lower order B) are through-connected and combined at the output side to form STM-N signals, positive/zero/negative pulse stuffing must be carried out herein and in a virtual container such as VC-3 (in the region of higher order A) or VC-4 wherein the through-connected virtual container was accommodated.
In a network of the synchronous digital hierarchy SDH, a synchronous clock pulse must be available at every network node, this synchronous clock pulse being synchronous with the network node to which the frequency normal is allocated.
The synchronous clock pulse could be distributed over a separate line network. However, it could also be derived from the clock frequency of the synchronous transport modules deriving from the network node having the frequency normal. This, however, is not exactly possible when a network node in the feeder link remains in the hold-over mode and generates its clock itself. An earlier proposal (German application P 40 33 557.7, incorporated herein) therefore proposes that the clock of a virtual container which is contained in a STM-N signal that arrives proceeding from the network node having the frequency normal is employed as a synchronizing signal. The clock frequency is derived from that of the frequency normal, and has the same frequency stability as the frequency normal.